Single Event Latch-up Effect of 130 nm Bulk Silicon CMOS Device Irradiated by Pulsed Laser
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摘要: 基于130nm体硅CMOS工艺，设计了具有不同阱/衬底接触与MOS管有源区间距、NMOS有源区与PMOS有源区间距的反相器链，利用脉冲激光试验开展了不同设计和不同工作电压下CMOS电路的单粒子闩锁效应敏感性研究.结果表明，随着阱/衬底接触与MOS管有源区的间距减小，以及NMOS与PMOS有源区间距的增大，电路抗SEL效应能力增强.此外，不同工作电压下电路的SEL效应规律表明，电压越大，反相器电路的SEL电流越大，且随着阱/衬底接触与MOS管有源区间距的减小以及NMOS与PMOS有源区间距的增大，电路出现SEL效应的开启电压增大.结合CMOS中寄生结构和单粒子闩锁效应触发机制，分析了相关因素影响电路单粒子闩锁效应敏感性的内在机制.Abstract: Based on the 130nm bulk silicon CMOS (Complementary Metal Oxide Semiconductor) process, inverter chains with different distance between well/substrate contact and MOS active, and the distance between NMOS active and PMOS active was designed. The Single Event Latch-up (SEL) characters of circuits with different designs and under various operation voltage were studied using the experiment of pulsed laser. Researches show that circuits will have higher sensitivity on SEL effect with the decrease of the distance between the well/substrate contact and the increase of the active distance between NMOS and PMOS. The decrease of the distance between the well/substrate contact and the active region of the MOS transistor represents the decrease of the well equivalent resistance and the substrate equivalent resistance. Therefore, a large induced current is needed to generate enough voltage drop to turn on the parasitic bipolar junction transistor, which eventually results in SEL effect. The increase of the active distance between NMOS and PMOS will reduce the partial voltage of the well parasitic resistance and the substrate parasitic resistance, which makes the parasitic bipolar junction transistor not easy to be triggered, so the SEL effect occurs difficultly. In addition, the SEL current increases with the increase of the operating voltage. Based on the parasitic structure in CMOS and the triggering mechanism of the SEL effect, the internal mechanism of related factors affecting the SEL sensitivity of circuits is analyzed.
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Key words:
- Single event latch-up /
- CMOS /
- Pulsed laser
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