Software–Hardware Co-Designed Fault-Tolerance and Optimization for a Spaceborne CNN FPGA Accelerator
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摘要: 针对星载计算平台在资源受限和抗辐射可靠性方面的双重需求,本文提出了一种面向卷积神经网络推理的 FPGA 软硬件协同容错加速器。该加速器采用 INT8/FP16 混合精度量化,以提升算力密度与计算效率;同时构建了软硬件分级容错机制以增强系统可靠性。其中,软件层通过异构双分支结构和置信度评估器抑制数据通路扰动,硬件层则对控制器、状态机等关键控制逻辑实施三模冗余(TMR)加固,以降低控制通路单点故障带来的影响。实验结果表明,在 XC7VX690T 平台部署 VGG-16 网络时,该加速器吞吐率达到 226.4 GOPS,推理时延为 136.52 ms,底层计算阵列平均有效执行效率达到 81.5%;并在故障注入条件下,系统仍能保持较高的分类准确率,表明所提方法能够满足星载边缘计算场景下对高效、可靠智能推理的应用需求。Abstract: To address the dual challenges of limited on-board resources and radiation reliability requirements in spaceborne computing platforms, this paper proposes an FPGA-based software–hardware co-designed fault-tolerant accelerator for convolutional neural network inference. The accelerator employs INT8/FP16 mixed-precision quantization to improve computational density and execution efficiency, while a hierarchical software–hardware fault-tolerance scheme is introduced to enhance system reliability. Specifically, at the software level, an asymmetric dual-branch architecture together with a confidence evaluator is adopted to suppress disturbances in the data path. At the hardware level, triple modular redundancy (TMR) is applied to critical control logic, including the controller and finite state machine (FSM), to mitigate the impact of single-point faults in the control path. Experimental results show that, when deploying the VGG-16 network on the XC7VX690T platform, the proposed accelerator achieves a throughput of 226.4 GOPS, an inference latency of 136.52 ms, and an average effective execution efficiency of 81.5% for the underlying computing array. Under fault injection conditions, the system still maintains high classification accuracy, demonstrating that the proposed method can satisfy the requirements for efficient and reliable intelligent inference in spaceborne edge computing scenarios.
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