Single Event Latch-up Effect of 130 nm Bulk Silicon CMOS Device Irradiated by Pulsed Laser

Based on the 130nm bulk silicon CMOS (Complementary Metal Oxide Semiconductor) process, inverter chains with different distance between well/substrate contact and MOS active, and the distance between NMOS active and PMOS active was designed. The Single Event Latch-up (SEL) characters of circuits with different designs and under various operation voltage were studied using the experiment of pulsed laser. Researches show that circuits will have higher sensitivity on SEL effect with the decrease of the distance between the well/substrate contact and the increase of the active distance between NMOS and PMOS. The decrease of the distance between the well/substrate contact and the active region of the MOS transistor represents the decrease of the well equivalent resistance and the substrate equivalent resistance. Therefore, a large induced current is needed to generate enough voltage drop to turn on the parasitic bipolar junction transistor, which eventually results in SEL effect. The increase of the active distance between NMOS and PMOS will reduce the partial voltage of the well parasitic resistance and the substrate parasitic resistance, which makes the parasitic bipolar junction transistor not easy to be triggered, so the SEL effect occurs difficultly. In addition, the SEL current increases with the increase of the operating voltage. Based on the parasitic structure in CMOS and the triggering mechanism of the SEL effect, the internal mechanism of related factors affecting the SEL sensitivity of circuits is analyzed.