Design and Implementation of a High-performance Image Compression Core for Spaceborne Applications

To address the critical need for efficient image storage and transmission in aerospace applications, this study presents a CCSDS 122.0-B-1-compliant compression core implemented on FPGA. The design incorporates innovative encoding control logic and optimized data organization through co-optimization of algorithmic features and hardware constraints. A segment-based architecture with 256-pixel blocks achieves superior compression efficiency among existing solutions, while effectively containing error propagation through segmented compression. The architecture further enables continuous quality adaptation and progressive image transmission. To resolve performance bottlenecks in scanning and encoding processes, fully parallelized scanning with adaptive parallel encoding was developed, and a 50% efficiency improvement was demonstrated in validation tests. Supporting images up to 4096×4096 pixel with 16-bit depth, the core delivers 90.64×10⁶sample·s^–1 throughput, meeting operational requirements for diverse space missions.